The present invention relates in general to a method for testing a semiconductor integrated circuit in which a current value of a xe2x80x9cstaticxe2x80x9d time power source current is measured with the help of an IC tester and whether or not the semiconductor integrated circuit has a defective portion generated in the manufacturing process is determined based on this result. More particularly, the invention relates to a method and an apparatus for testing a semiconductor integrated circuit that has a complementary metal oxide semiconductor element (CMOS) structure.
In a manufacturing process of a semiconductor integrated circuit such as an IC, an LSI, etc. having a CMOS structure, it has conventionally determined whether or not the semiconductor integrated circuit contains a defective portion which occurs in the manufacturing process. By doing so the efficiency of the manufacturing process thereafter can be increased.
Determination of whether or not a defective portion is contained in the semiconductor integrated circuit is generally performed using an IC tester. There are various kinds of sorting methods (testing methods) that use an IC tester. For example, there is a method of measuring the current value of the power source current (hereinafter called xe2x80x9ca static-time power source currentxe2x80x9d) that flows when the IC is out of operation and determining according to this measured current value whether or not a defective portion is contained in the semiconductor integrated circuit.
In this method where connecting an IC tester to this semiconductor integrated circuit of CMOS structure and measuring the power source current of this circuit, the resulting circuit construction becomes the one (hereinafter called xe2x80x9ca CMOS transistorxe2x80x9d) in which a PMOS transistor and a NMOS transistor are connected in series in the form of a totem pole between the power source and the ground of the tester for measuring the current. Therefore, any one of the PMOS transistor or the NMOS transistor can be made off by fixing each of the respective input terminals of the semiconductor integrated circuit to the power source level or the ground level by means of the tester. It thereby becomes possible to measure the static time power source current. In this case, putting aside a case where the IC has an internal circuit that, even when the IC is kept in the non-operating state, permits a power source current to flow there through, the static-time power source current of the semiconductor integrated circuit usually becomes the sum total of the current values that flow when the CMOS transistors made up on this circuit are being kept xe2x80x9coffxe2x80x9d. However, this sum total value is very small, and in many cases is on the order of xcexcA or less.
Generally, in the manufacturing process of a semiconductor, when some drawback occurs in this process, an unnecessary current path is formed in the internal circuit of the semiconductor integrated circuit. In the semiconductor integrated circuit having such an unnecessary current path, even when the CMOS transistor is kept in the non-operating state, the power source current flows into the unnecessary current path that has been formed. The power source current that flows into this unnecessary current path is added to the static-time power source current. For this reason, the current value of the static-time power source current that has been measured when the unnecessary current path has been formed becomes larger than that of the static-time power source current that has been measured when no unnecessary current path has been formed.
Such an unnecessary current path increases the current value of the static-time power source current that flows when the IC is in the non-operating state. Therefore, in addition to increasing the power consumption of the semiconductor integrated circuit, it hinders the normal function and operation thereof even when the semiconductor integrated circuit is in operation. Therefore, the semiconductor integrated circuit that has this unnecessary current path is determined as a defective product.
When performing determination of the defective product of the semiconductor integrated circuit by measurement of the current value of the static-time power source current, ordinarily, it was practiced to fix the internal circuit of the semiconductor integrated circuit to a certain logical state and then perform the measurement once, or it was practiced to change the logical state and perform the measurement a plurality of times. Then, the measured current value is compared with a standard value that is one absolute value, whereby it is determined according to the compared result whether or not the semiconductor integrated circuit was a defective product with an unnecessary current path.
FIG. 11 illustrates a circuit diagram of a conventional static-time power source current measuring circuit with respect to the semiconductor integrated circuit. In FIG. 11, one end of a semiconductor integrated circuit 101 to be measured such as an ASIC is grounded, while the other end thereof is connected to a current measuring instrument 102. A power source 103 is grounded at one end and is connected at the other end to the current measuring instrument 102. A voltage VDD is thereby applied from the power source 103 to the semiconductor integrated circuit 101 through the current measuring instrument 102, and a current is thereby supplied to the circuit 101. On the other hand, a test pattern 105 for setting a logical state is input to the semiconductor integrated circuit 101. It is thereby possible to set the state of connection in the internal circuit of the semiconductor integrated circuit 101 variously. In the state of connection that has been so set by this test pattern, the current measuring instrument 102 measures the current value IDD. And it is determined according to this measured current value IDD whether or not an unnecessary current path exists within the semiconductor integrated circuit 101.
FIGS. 12A and 12B illustrate in block diagram form an example of the internal circuit within the semiconductor integrated circuit 101 and an unnecessary current path therein. FIGS. 12A and 12B illustrate an inverter circuit whose PMOS transistor 113 and NMOS transistor 114 are connected in series to each other. FIG. 12A illustrates a case where, by the test pattern 105 being applied to their gate, the PMOS transistor 113 has been set to an xe2x80x9coffxe2x80x9d state and the NMOS transistor 114 has been set to an xe2x80x9conxe2x80x9d state. FIG. 12B illustrates a case where, by the test pattern 105 being applied to their gate, the PMOS transistor 113 has been set to an xe2x80x9conxe2x80x9d state and the NMOS transistor 114 has been set to an xe2x80x9coffxe2x80x9d state. In FIG. 12A, when an unnecessary current path 115 exists between the power source 103 and the drain of the PMOS transistor 114, it results that an unnecessary current flows between the power source 103 and the ground 104. At this time, the-current according to the ability of the NMOS transistor 114 flows between the power source 103 and the ground 104. Similarly, in FIG. 12B, when an unnecessary current path 115 exists between the ground 104 and the drain of the NMOS transistor 114, it results that an unnecessary current flows between the power source 103 and the ground 104. At this time, the current according to the ability of the PMOS transistor 113 flows between the power source 103 and the ground 104.
In the semiconductor integrated circuit of CMOS structure, when each of its respective signals including a clock signal changes, i.e., rises or falls, a pass current and charge and discharge currents of the load capacitor temporarily flow by both the PMOS transistor and the NMOS transistor being made xe2x80x9conxe2x80x9d. Since this state is temporary, these currents gradually decrease. Then, in a state where each signal has thereafter been fixed, these currents cease to flow. Namely, the logical state of the internal circuit is set as is so by the test pattern that is input to each of the respective input terminals thereof, and the power source current thereof temporarily increases when each signal is changed. Ordinarily, when the active edge of either the rise or the fall of the clock signal is changed, the internal flip flops operate all together, whereby the signal lines that are connected with the flip flops begins to change all together. Therefore, a largest amount of power source current flows. FIG. 13 illustrates a timing chart of the relationship between one clock signal of the test pattern 105 input to the semiconductor integrated circuit 101 and a power source current value IDD. Namely, the FIG. 13 illustrates an example when the internal flip flops work all together by the rise of the clock signal, and the power source current value IDD is temporarily increased. In this case, the time length within one period, during which the logical state of the internal circuit is kept fixed, is a static time (t1) of the semiconductor integrated circuit 101. Ordinarily, the measurement of the static-time power source current is performed at the static time of the semiconductor integrated circuit 101 that succeeds a time (t2) during which the changes in all signals, including the clock signal, that have been input, are completed and one logical state has thereby been set, namely, at the time (t1) in which the logical state of the internal circuit has become stable. In FIG. 13, at the time of P(1) and P(2), the current value IDD of the static-time power source current is measured.
FIG. 14 illustrates a timing chart of a change of the power source current value IDD according to the passage of time that prevails when measurement is made a plurality of times. In FIG. 14, using the test pattern 105, logical setting is done as the test period a plurality of times. In FIG. 14, logical setting is done with j-time periods. Measurement of the current value of the static-time power source current is performed at the static time (t1) after logical setting has been done. It is to be noted that in FIG. 14 illustration is also made together of a standard value IDD1 that is an absolute reference value for determining whether or not the semiconductor integrated circuit 101 contains a defective portion therein, an average value Iave1 of the static-time power source currents that are obtained when no defective CMOS element exists, and a dispersion range xcex94TR1 of the static-time power source current values that have been measured from the semiconductor integrated circuit itself and that contain the measurement errors.
As shown in FIG. 14, the current values IDD at the time of P(1) and P(2) are both less than the standard value IDD1, and therefore it is determined that no unnecessary current path exists. However, the current value IDD at the time of P(3) exceeds the standard value IDD1, and therefore it is determined that an unnecessary current path exists in the circuit in this logical setting. Then, the semiconductor integrated circuit 101 having one unnecessary current path is determined as being a defective product.
The series of this test processing is as follows. First, the test pattern 105 works the semiconductor integrated circuit, and the logical state inside is determined (t2). Thereafter, the current value IDD of the static-time (t1) power source current is measured. This current value IDD is compared with the standard value IDD1. In a case where the current value IDD does not exceed the standard value IDD1, the test pattern 105 is further supplied to the semiconductor integrated circuit 101 to thereby determine a logical state thereof. After this determined logical state, the current value IDD of the static-time power source current is measured again. This re-measured current value IDD and the standard value IDD1 are compared with each other. When the current value IDD has exceeded the standard value IDD1 during this repetition of such comparison processing, it is decided, at this point, that an unnecessary current circuit exists in the semiconductor integrated circuit 101. And it is determined that the semiconductor integrated circuit 101 is a defective product, and succeeding measurement and comparison processing are not performed thereafter. On the other hand, when the current value IDD does not exceed the standard value IDD1 even when the measurement and the comparison is performed for the predetermined number of times then the semiconductor integrated circuit 101 is determined to be a non-defective product.
Namely, in this testing method of a semiconductor integrated circuit, if every comparison result is that: IDD less than IDD1, it is determined that the semiconductor integrated circuit is a non-defective product. And if equal to or more than one comparative result is that:
IDDxe2x89xa7IDD1, 
it is determined that the semiconductor integrated circuit is a defective product.
Meanwhile, assuming that xe2x80x9cIdd(tr)xe2x80x9d represents the current value of the static-time power source current of one transistor; xe2x80x9cxcex94Idd(tr)xe2x80x9d represents the dispersion of this current value; and the semiconductor integrated circuit 101 as a whole has an N number of transistors, the current value IDD (static) of the static-time power source current of the entire semiconductor integrated circuit 101 which does not have unnecessary current path can be expressed as follows.
IDD(static)=Idd(tr)xc2x7N+xcex94Idd(tr)xc2x7N 
At this time, the current value IDD (measure) of the measured static-time power source current can be expressed, under the assumption that xe2x80x9cxcex94Idd (measure)xe2x80x9d represents the measurement error, as follows.
IDD(measure)=IDD(static)+xcex94Idd(measure) 
Also, assuming that xe2x80x9cxcex94Idd (fault)xe2x80x9d represents a portion of change in current due to the unnecessary current path, the, current value IDD (fault) of the static-time power source current of the entire semiconductor integrated circuit 101 which has an unnecessary current path is expressed as follows.
IDD(fault)=IDD(static)+xcex94Idd(fault) 
At this time, when comparing the measurement error xcex94Idd (measure), and the portion of change in current xcex94Idd (fault) due to the unnecessary current path, of the semiconductor integrated circuit 101, if the scale of the semiconductor integrated circuit 101 is small, the following equation holds true.
xcex94Idd(fault) greater than  greater than xcex94Idd(measure) 
Therefore, it is possible to clearly distinguish between the portion of change in current xcex94Idd (fault) and the measurement error xcex94Idd (measure). And therefore,
IDD(measure)(=IDD(static)+xcex94Idd(measure)) 
 less than  less than IDD(fault)(=IDD(static)+xcex94Idd(fault)) 
Here, FIG. 15 illustrates a graph of an example of the dispersion range of the current values IDD of the static-time power source current. In FIG. 15, it can be seen that when the average value (that is indicated by the round black dot xe2x80x9cxe2x97xafxe2x80x9d) of the current values IDD of the static-time power source current is small, the dispersion range of the current values is also small. For example, each of the average values of samples A, B, and D are each below the standard value IDD1, and are small. In addition, the dispersion ranges xcex94Ia1, xcex94Ib1, and xcex94Id1 also are each small. In contrast to this, the average value of a sample C exceeds the standard value IDD1, and the dispersion range xcex94Ic1 is also large.
Accordingly, when each of the current values Idd(tr)xc2x7N of the static-time power source current are small, each of the values of the dispersion xcex94Idd(tr)xc2x7N in the semiconductor integrated circuit itself also becomes small. Therefore, by setting the standard value IDD1 as one value that satisfies the equation:
IDD(static)(≈Idd(tr)xc2x7N) less than IDD(measure) less than IDD1 less than IDD(fault) 
and comparing the current value IDD (measure) of the static-time power source current to the standard value IDD1, it is possible to determine whether an unnecessary current path is present, i.e., whether the semiconductor integrated circuit is a defective product.
However, with technical progress that has been made in recent years, it has, in actuality, become possible to manufacture more and more speedy and highly integrated and larger-in-scale semiconductor integrated circuits. In these speedy and highly integrated and larger-in-scale semiconductor integrated circuits, the current values Idd(tr) of the static-time power source current between the respective transistors constituting the semiconductor integrated circuit, and the dispersion xcex94Idd(tr) of these current values have become large. Further, the dispersion xcex94Idd(IC) between the respective semiconductor integrated circuits due to the process parameters used in manufacturing the semi conductor IC""s also has become large. This is accompanied by the dispersion xcex94Idd(IC) between the semiconductor integrated circuits and the portion of change in current xcex94Idd (fault) due to the unnecessary current path becoming almost equal to each other, or to the dispersion xcex94Idd(IC) exceeding the portion of change in current xcex94Idd (fault). Therefore, in the conventional testing method of a semiconductor integrated circuit, distinguishing between the dispersion and the portion of change in current becomes difficult, and there is a problem that it is not possible to accurately determine whether the semiconductor integrated circuit is a defective product.
Namely, the static-time power source current IDD (static) (=Idd(tr)xc2x7N+xcex94Idd(tr)xc2x7N) itself in the semiconductor integrated circuit which does not have unnecessary current path is largely dispersed between the semiconductor integrated circuits. Therefore, even in the case of the static-time power source current IDD (static) free from any unnecessary current path, when it is compared with the static-time power source current IDD (fault) in another semiconductor integrated circuit which has an unnecessary current path, there occurs a case wherein:
IDD(static)xe2x89xa7IDD(fault) 
In this case, even when using the standard value IDD1 that is one absolute reference value, it is impossible to detect reliably the presence or the absence of an unnecessary current path. Therefore, there is a problem that it is resultantly difficult to perform a determination of whether or not the semiconductor integrated circuit is a defective product.
It is an object of the present invention to provide a method for testing a semiconductor integrated circuit which enables the reliable detection of the drawback that has occurred in the manufacturing process of a semiconductor by measuring the current value of the static-time power source current, even in the case of a semiconductor integrated circuit wherein the current values of the static-time power source current of each of the respective elements constituting the semiconductor integrated circuit, and the dispersion of these current values, are large; and further the dispersion between the semiconductor integrated circuits due to the process parameters is large.
In a testing method of semiconductor integrated circuit, according to the first aspect of this invention, a current value of a static-time power source current passing through a plurality of elements that constitute a semiconductor integrated circuit is measured for a plurality of times while sequentially changing and setting a logical state of the plurality of elements. Further, maximum and minimum values are extracted from the plurality of the current values that have been measured. Further, it is determined that the semiconductor integrated circuit is a defective product when the difference between the maximum and the minimum values exceeds a predetermined value.
In a testing method of semiconductor integrated circuit according to the second aspect of this invention, a current value of a static-time power source current passing through a plurality of elements that constitute a semiconductor integrated circuit is measured for a plurality of times while changing and setting a logical state of the plurality of elements. Further, a difference between the successively measured current values with respect to a plurality of current values that have been measured is calculated. Further, it is determined that the semiconductor integrated circuit is a defective product when at least one of the calculated difference exceeds a predetermined value.
In a testing method of semiconductor integrated circuit according to the third aspect of this invention, a current value of a static-time power source current passing through a plurality of elements that constitute a semiconductor integrated circuit is measured in a first measuring step while changing and setting a logical state of the plurality of elements. Further, a current value of the static-time power source current passing through the plurality of elements that constitute the semiconductor integrated circuit is measured in a second measuring step while changing and setting a logical state of the plurality of elements set in the first measuring step. Further, a difference between the current values measured in the first and second measuring steps is calculated. Further, it is determined that the semiconductor integrated circuit is a defective product when the calculated difference exceeds a predetermined value. Further, when it is determined that the semiconductor integrated circuit is a non-defective product then the current value obtained in the second measuring step is replaced with the current value obtained in the first measuring step and the second measuring step, the calculation of difference and the determination of defectiveness is repeated for a predetermined number of times.
In a testing method of semiconductor integrated circuit according to the fourth aspect of this invention, a current value of a static-time power source current passing through a plurality of elements that constitute a semiconductor integrated circuit is measured for a plurality of times while sequentially changing and setting a logical state of the plurality of elements. Further, a standard deviation of the plurality of the measured current values is calculated. Further, it is determined that the semiconductor integrated circuit is a defective product when the standard deviation exceeds a predetermined value.
In a testing method of semiconductor integrated circuit according to the fifth aspect of this invention, a current value of a static-time power source current passing through a plurality of elements that constitute a semiconductor integrated circuit is measured for a plurality of times while sequentially changing and setting a logical state of the plurality of elements. Further, maximum and minimum values are extracted from the measured current values. Further, an average of the measured current values is calculated. Further, it is determined that the semiconductor integrated circuit is a defective product when a difference between the average and the maximum value and a difference between the average and the minimum value exceeds a predetermined value.
In a testing method of semiconductor integrated circuit according to the sixth aspect of this invention, a logical state of the elements is set to an initial state, the current value of a static-time power source current is measured, when the difference between the current value at the time of initial logical state and the current value after re-setting is greater than a predetermined value then it is determined that the semiconductor integrated circuit is a non-defective product.
In an apparatus for testing a semiconductor integrated circuit, according to the seventh aspect of this invention, a measuring unit measures a current value of a static-time power source current passing through a plurality of elements that constitute a semiconductor integrated circuit for a plurality of times while sequentially changing and setting a logical state of the plurality of elements. Further, an extracting unit extracts maximum and minimum values from the plurality of the current values that have been measured. Further, a determining unit determines that the semiconductor integrated circuit is a defective product when the difference between the maximum and the minimum values exceeds a predetermined value.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.